(China (Mainland))
Product Summary
The ADSP-21020BG-80 is a single-chip IEEE floating-point processors optimized for digital signal processing applications. Its architecture is similar to that of Analog Devices’ ADSP-2100 family of fixed-point DSP processors. Fabricated in a high-speed, low-power CMOS process, the ADSP-21020BG-80 has a 30 ns instruction cycle time. With a highperformance on-chip instruction cache, the ADSP-21020BG-80 can execute every instruction in a single cycle.
Parametrics
ADSP-21020BG-80 absolute maximum ratings: (1)Supply Voltage: -0.3 V to +7 V; (2)Input Voltage: -0.3 V to VDD + 0.3 V; (3)Output Voltage Swing: -0.3 V to VDD + 0.3 V; (4)Load Capacitance: 200 pF; (5)Operating Temperature Range (Ambient): -55℃ to +125℃; (6)Storage Temperature Range: -65℃ to +150℃; (7)Lead Temperature (10 seconds) CPGA: +300℃.
Features
ADSP-21020BG-80 features: (1)Superscalar IEEE Floating-Point Processor; (2)Off-Chip Harvard Architecture Maximizes Signal Processing Performance; (3)30 ns, 33.3 MIPS Instruction Rate, Single-Cycle Execution; (4)100 MFLOPS Peak, 66 MFLOPS Sustained Performance; (5)1024-Point Complex FFT Benchmark: 0.58 ms; (6)Divide (y/x): 180 ns; (7)Inverse Square Root (1/√X): 270 ns; (8)32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats; (9)32-Bit Fixed-Point Formats, Integer and Fractional, with 80-Bit Accumulators; (10)IEEE Exception Handling with Interrupt on Exception; (11)Three Independent Computation Units: Multiplier, ALU, and Barrel Shifter; (12)Dual Data Address Generators with Indirect, Immediate, Modulo, and Bit Reverse Addressing Modes; (13)Two Off-Chip Memory Transfers in Parallel with Instruction Fetch and Single-Cycle Multiply & ALU Operations; (14)Multiply with Add & Subtract for FFT Butterfly Computation; (15)Efficient Program Sequencing with Zero-Overhead Looping: Single-Cycle Loop Setup; (16)Single-Cycle Register File Context Switch; (17)15 (or 25) ns External RAM Access Time for Zero-Wait-State, 30 (or 40) ns Instruction Execution; (18)IEEE JTAG Standard 1149.1 Test Access Port and On-Chip Emulation Circuitry; (19)223-Pin PGA Package (Ceramic).
Diagrams
