EP1K100QC208-1N

Product Summary

The EP1K100QC208-1N is a single-device, high-speed, advanced configuration solution for very high-density FPGAs. The core of an enhanced configuration device is divided into two major blocks: a configuration controller and a flash memory. The flash memory is used to store configuration data for systems made up of one or more Altera FPGAs. Unused portions of the flash memory of the EP1K100QC208-1N can be used to store processor code or data that can be accessed via the external flash interface after FPGA configuration is complete.

Parametrics

EP1K100QC208-1 absolute maximum ratings: (1)VCC Supply voltage With respect to ground: -0.2V to 4.6 V; (2)VI DC input voltage With respect to ground: -0.5V to 3.6 V; (3)IMAX DC VCC or ground current: 100mA; (4)IOUT DC output current, per pin: -25mA to 25mA; (5)PD Power dissipation: 360mW; (6)TSTG Storage temperature No bias: -65℃ to 150℃; (7)TAMB Ambient temperature Under bias -65℃ to 135℃; (8)TJ Junction temperature Under bias: 135℃.

Features

EP1K100QC208-1N features: (1)Single-chip configuration solution for AlteraR ACEXR 1K, APEX 20K (including APEX 20K, APEX 20KC, and APEX 20KE), APEX II, ArriaR GX, CycloneR, Cyclone II, FLEXR 10K (including FLEX 10KE and FLEX 10KA), Mercury, StratixR II, and Stratix II GX devices; (2)Contains 4-, 8-, and 16-Mbit flash memories for configuration data storage; (3)On-chip decompression feature almost doubles the effective configuration density; (4)Standard flash die and a controller die combined into single stacked chip package; (5)External flash interface supports parallel programming of flash and external processor access to unused portions of memory; (6)Flash memory block/sector protection capability via external flash interface; (7)Supported in EPC16 and EPC4 devices; (8)Page mode support for remote and local reconfiguration with up to eight configurations for the entire system; (9)Compatible with Stratix series Remote System Configuration feature; (10)Supports byte-wide configuration mode fast passive parallel (FPP); 8-bit data; (11)output per DCLK cycle; (12)Supports true n-bit concurrent configuration (n = 1, 2, 4, and 8) of Altera FPGAs; (13)Pin-selectable 2-ms or 100-ms power-on reset (POR) time; (14)Configuration clock supports programmable input source and frequency synthesis; (15)Multiple configuration clock sources supported (internal oscillator and external clock input pin); (16)External clock source with frequencies up to 100 MHz; (17)Internal oscillator defaults to 10 MHz; Programmable for higher frequencies of 33, 50, and 66 MHz; (18)Clock synthesis supported via user programmable divide counter; (19)Available in the 100-pin plastic quad flat pack (PQFP) and the 88-pin Ultra FineLine BGAR (UFBGA) packages; (20)Vertical migration between all devices supported in the 100-pin PQFP package; (21)Supply voltage of 3.3 V (core and I/O); (22)Hardware compliant with IEEE Std. 1532 in-system programmability (ISP) specification; (23)Supports ISP via Jam Standard Test and Programming Language (STAPL); (24)Supports JTAG boundary scan; (25)nINIT_CONF pin allows private JTAG instruction to start FPGA configuration; (26)Internal pull-up resistor on nINIT_CONF always enabled; (27)User programmable weak internal pull-up resistors on nCS and OE pins; (28)Internal weak pull-up resistors on external flash interface address and control lines, bus hold on data lines; (29)Standby mode with reduced power consumption.

Diagrams