XC95288XL-10FGG256C

High-Performance CPLD, BGA, 3.3V, 208 MHz, Xilinx, XC95288XL-10FGG256C

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Price:: US $3.00~10.00 / piece [Get Latest Price]

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PartNumber:: XC95288XL-10FGG256C

Brand:: Xilinx, Inc - Xilinx | Pack: BGA | D/C: 06+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-05-07

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Part Number:XC95288XL-10FGG256C
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Product Summary

The XC95288XL-10FGG256C is a High-Performance CPLD. The XC95288XL-10FGG256C is targeted for high-performance, low-voltage applications in leading-edge communications and computing systems, where high device reliability and low power dissipation is important. The XC95288XL-10FGG256C architectural features address the requirements of in-system programmability. Enhanced pin-locking capability avoids costly board rework. In-system programming throughout the full commercial operating range and a high programming endurance rating provide worry-free reconfigurations of system field upgrades. Extended data retention supports longer and more reliable system operating life.

Parametrics

XC95288XL-10FGG256C absolute maximum ratings: (1)VCC, Supply voltage relative to GND: –0.5 to 4.0 V; (2)VIN, Input voltage relative to GND: –0.5 to 5.5 V; (3)VTS, Voltage applied to 3-state output: –0.5 to 5.5 V; (4)TSTG, Storage temperature (ambient): –65 to +150℃; (5)TSO,L Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm): +260℃; (6)TJ, Junction temperature: +150℃.

Features

XC95288XL-10FGG256C features: (1)5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz; (2)Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package); (3)Pb-free available for all packages; (4)Lower power operation; (5)5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals; (6)3.3V or 2.5V output capability; (7)Advanced 0.35 micron feature size CMOS FastFLASH technology; (8)In-system programmable; (9)Superior pin-locking and routability with FastCONNECT II. switch matrix; (10)Extra wide 54-input Function Blocks; (11)Up to 90 product-terms per macrocell with individual product-term allocation.