(China (Mainland))
Product Summary
The 5962-8751601CA is a dual positive-edge-triggered D-type flip-flop. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup-time requirements of the 5962-8751601CA is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at D can be changed without affecting the levels at the outputs.
Parametrics
5962-8751601CA absolute maximum ratings: (1)Supply voltage range, VCC: -0.5 V to 7 V; (2)Input voltage range, VI: -0.5 V to VCC + 0.5 V; (3)Output voltage range, VO: -0.5 V to VCC + 0.5 V; (4)Input clamp current, IIK (VI < 0 or VI > VCC): ±20 mA; (5)Output clamp current, IOK (VO < 0 or VO > VCC): ±20 mA; (6)Continuous output current, IO (VO = 0 to VCC): ±50 mA; (7)Continuous current through VCC or GND: ±200 mA; (8)Package thermal impedance, θJA (see Note 2): D package: 86℃/W; (9)Storage temperature range, Tstg: -65℃ to 150℃.
Features
5962-8751601CA features: (1)4.5-V to 5.5-V VCC Operation; (2)Inputs Accept Voltages to 5.5 V; (3)Max tpd of 10.5 ns at 5 V; (4)Inputs Are TTL-Voltage Compatible.
Diagrams
