LU82541PI

LU82541PI, single, compact component, BGA, 3.3V, VSS -0.5V to 4.6V, Intel Corporation

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Price:: US $0.65~1.00 / piece [Get Latest Price]

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Qty (lots)	Price/lot
1 ~ 100 :	1.00 / Piece
101 ~ 500 :	0.80 / Piece
501 ~ 1000 :	0.65 / Piece

PartNumber:: LU82541PI

Brand:: Intel Corporation - Intel | Pack: BGA | D/C: 03+

Availability:: Supply Ability: 2/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

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Products Upload time: 2012-12-24

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Part Number:LU82541PI
US $0.65 - 1.00
Quantity:

piece

Product Summary

The LU82541PI is a single, compact component with an integrated Gigabit Ethernet Media Access Control (MAC) and physical layer (PHY) functions. For desktop, workstation and mobile PC Network designs with critical space constraints, the LU82541PI allows for a Gigabit Ethernet implementation in a very small area that is footprint compatible with current generation 10/100 Mbps Fast Ethernet designs. The LU82541PI incorporates the Clock Run protocol and hardware supported downshift capability to two-pair and three-pair 100 Mbps operation. These features optimize mobile applications.

Parametrics

LU82541PI absolute maximum ratings: (1)VDD (3.3) DC supply voltage on 3.3 V pins with respect to VSS: VSS - 0.5 to 4.6 V; (2)VDD (1.8) DC supply voltage on 1.8 V pins with respect to VSS: VSS-0.5V to 2.5 or VDD (1.8) + 0.5b V; (3)VDD (1.2) DC supply voltage on 1.2 V pins with respect to VSS: VSS - 0.5 1.7 or VDD (1.2) + 0.5c V; (4)VDD DC supply voltage: VSS-0.5 to 4.6V; (5)VI / VO Input voltage: VSS-0.5V to 4.6V; (6)IO Output current: 40mA; (7)TSTG Storage temperature range: -40 to 125℃.

Features

LU82541PI features: (1)PCI revision 2.3, 32-bit, 33/66 MHz; (2)Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands; (3)CLK_RUN# signal; (4)3.3 V (5 V tolerant PCI signaling); (5)Low-latency transmit and receive queues; (6)IEEE 802.3x-compliant flow-control support with software-controllable thresholds; (7)Caches up to 64 packet descriptors in a single burst; (8)Programmable host memory receive buffers (256 B to 16 KB) and cache line size (16 B to 256 B); (9)Wide, optimized internal data path architecture; (10)64 KB configurable Transmit and Receive FIFO buffers; (11)Four programmable LED outputs; (12)On-chip power regulator control circuitry; (13)BIOS LAN Disable pin; (14)JTAG (IEEE 1149.1) Test Access Port built in silicon (3.3 V, 5 V tolerant PCI signaling).