LM3S6432-IQC50-A2

Product Summary

The LM3S6432-IQC50-A2 is a microcontroller. It is based on the ARM controller core operating at up to 50 MHz, with 96 kB flash and 32 kB SRAM. The LM3S6432-IQC50-A2 also features real-time industrial connectivity, with a 10/100 Ethernet MAC/PHY, an SSI / SPI controller, an I2C interface, and 2 UARTs. The LM3S6432-IQC50-A2 microcontroller also features advanced motion control features, including 2 motion-control PWM outputs with dead-band and 1 fault protection inputs for low-latency shutdown. The microcontroller also features intelligent analog capability, including 2 analog comparators and 3 channels of highly accurate 10-bit analog-to-digital conversion - with the ability to sample at speeds of 250K samples per second.

Parametrics

LM3S6432-IQC50-A2 absolute maximum ratings: (1)I/O supply voltage (VDD) VDD: 0 to 4V; (2)Core supply voltage (VDD25) VDD25: 0 to 3V; (3)Analog supply voltage (VDDA) VDDA: 0 to 4V; (4)Ethernet PHY supply voltage (VCCPHY) VCCPHY: 0 to 4V; (5)Input voltage VIN: -0.3 to 5.5V; (6)Input voltage for a GPIO configured as an analog input: -0.3 to VDD + 0.3V; (7)Maximum current per output pins I: 25mA; (8)Maximum input voltage on a non-power pin when the microcontroller is un powered VNON: 300mV.

Features

LM3S6432-IQC50-A2 features: (1)System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism; (2)Thumb-compatible Thumb-2-only instruction set processor core for high code density; (3)50-MHz operation; (4)Hardware-division and single-cycle-multiplication; (5)Integrated Nested Vectored Interrupt Controller (NVIC)providing deterministic interrupt handling; (6)29 interrupts with eight priority levels; (7)Optimized for single-cycle flash usage; (8)Three sleep modes with clock gating for low power; (9)Single-cycle multiply instruction and hardware divide; (10)Atomic operations; (11)ARM Thumb2 mixed 16-/32-bit instruction set; (12)1.25 DMIPS/MHz.

Diagrams