(China (Mainland))
Product Summary
The IDT79R3081E-40MJ is a high-performance 32-bit microprocessor featuring a high-level of integration, and targeted to high-performance but cost sensitive processing applications. The IDT79R3081E-40MJ is designed to bring the highperformance inherent in the MIPS RISC architecture into low-cost, simplified, power sensitive applications. Thus, functional units have been integrated onto the CPU core in order to reduce the total system cost, rather than to increase the inherent performance of the integer engine. Nevertheless, the IDT79R3081E-40MJ is able to offer 43VUPS performance at 50MHz without requiring external SRAM or caches.
Parametrics
IDT79R3081E-40MJ absolute maximum ratings: (1)VTERM, Terminal Voltage with Respect to GND: -0.5 to +7.0V; (2)TC, Operating Case Temperature: 0 to +85℃; (3)TBIAS, Case Temperature Under Bias: -55 to +125℃; (4)TSTG, Storage Temperature: -55 to +125℃; (5)VIN, Input Voltage: -0.5 to +7.0V.
Features
IDT79R3081E-40MJ features: (1)Instruction set compatible with IDT79R3000A, R3041, R3051, and R3071 RISC CPUs; (2)High level of integration minimizes system cost, R3000A Compatible CPU; R3010A Compatible Floating Point Accelerator; Optional R3000A compatible MMU; Large Instruction Cache; Large Data Cache; Read/Write Buffers; (3)43VUPS at 50MHz, 13MFlops; (4)Flexible bus interface allows simple, low cost designs; (5)Optional 1x or 2x clock input; (6)20 through 50MHz operation; (7)"V" version operates at 3.3V; (8)50MHz at 1x clock input and 1/2 bus frequency only; (9)Large on-chip caches with user configurability, 16kB Instruction Cache, 4kB Data Cache; Dynamically configurable to 8kB Instruction Cache, 8kB Data Cache; Parity protection over data and tag fields; (10)Low cost 84-pin packaging; (11)Superset pin- and software-compatible with R3051, R3071; (12)Multiplexed bus interface with support for low-cost, lowspeed memory systems with a high-speed CPU; (13)On-chip 4-deep write buffer eliminates memory write stalls; (14)On-chip 4-deep read buffer supports burst or simple block reads; (15)On-chip DMA arbiter; (16)Hardware-based Cache Coherency Support; (17)Programmable power reduction mode; (18)Bus Interface can operate at half-processor frequency.
Diagrams
