IDT70V24S55PF

IDT70V24S55PF, high-speed 4K x 16 Dual-Port Static RAM, QFP, 50mA, -0.5V to +4.6V, 3.3V

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Price:: US $1.00~3.00 / piece [Get Latest Price]

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Qty (lots)	Price/lot
1 ~ 100 :	3.00 / Piece
200 ~ 300 :	2.00 / Piece
300 ~ 500 :	1.00 / Piece

PartNumber:: IDT70V24S55PF

Brand:: Integrated Device Technology - IDT | Pack: PQFP | D/C:

Availability:: Supply Ability: 2/Day Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Total Price:: US $0

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Products Upload time: 2012-12-24

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Part Number:IDT70V24S55PF
US $1.00 - 3.00
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piece

Product Summary

The IDT70V24S55PF is a high-speed 4K x 16 Dual-Port Static RAM. The IDT70V24S55PF is designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 32-bit-or-more word systems using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit or wider memory system applications results in full-speed, error-free operation without the need for additional discrete logic. The IDT70V24S55PF provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode.

Parametrics

IDT70V24S55PF absolute maximum ratings: (1)VTERM(2) Terminal Voltage with Respect to GND:–0.5 to +4.6V; (2)TA Operating Temperature: 0 to +70℃; (3)TBIAS Temperature Under Bias:–55 to +125℃; (4)TSTG Storage Temperature:–55 to +125℃; (5)IOUT DC Output Current: 50mA.

Features

IDT70V24S55PF features: (1)True Dual-Ported memory cells which allow simultaneous access of the same memory location; (2)High-speed access; (3)Commercial: 25/35/55ns (max.); (4)Low-power operation; (5)Separate upper-byte and lower-byte control for multiplexed bus compatibility; (6)IDT70V24 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device; (7)M/S = H for BUSY output flag on Master; (8)M/S = L for BUSY input on Slave; (9)Busy and Interrupt Flags; (10)Devices are capable of withstanding greater than 2001V electrostatic charge.; (11)On-chip port arbitration logic; (12)Full on-chip hardware support of semaphore signaling between ports; (13)Fully asynchronous operation from either port; (14)LVTTL-compatible, single 3.3V (±0.3V) power supply; (15)Available in 84-pin PGA, 84-pin PLCC, and 100-pin TQFP.