(China (Mainland))
Product Summary
The CD54HC164F3A is an 8-bit serial-in parallel-out shift registers with asynchronous reset. Data of the CD54HC164F3A is shifted on the positive edge of Clock (CP). A LOW on the Master Reset(MR) pin resets the shift register and all outputs go to the LOW state regardless of the input conditions. Two Serial Data inputs (DS1 and DS2) are provided, either one can be used as a Data Enable control.
Parametrics
CD54HC164F3A absolute maximum ratings: (1)DC Supply Voltage, VCC: -0.5V to 7V; (2)DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V: ±20mA; (3)DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V: ±20mA; (4)DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V: ±25mA; (5)DC VCC or Ground Current, ICC or IGND: ±50mA.
Features
CD54HC164F3A features: (1)Buffered Inputs; (2)Asynchronous Master Reset; (3)Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25℃; (4)Fanout (Over Temperature Range), Standard Outputs: 10 LSTTL Loads; Bus Driver Outputs: 15 LSTTL Loads; (5)Wide Operating Temperature Range: -55℃ to 125℃; (6)Balanced Propagation Delay and Transition Times; (7)Significant Power Reduction Compared to LSTTL Logic ICs; (8)HC Types, 2V to 6V Operation; High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V; (9)HCT Types, 4.5V to 5.5V Operation; Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min); (10)CMOS Input Compatibility, Il . 1μA at VOL, VOH.
Diagrams
