Product Summary

The CY7C140-30PC is a high-speed CMOS 1K by 8 dual-port static RAM. Two ports are provided permitting independent access to any location in memory. The CY7C130/ CY7C131 can be utilized as either a standalone 8-bit dual-port static RAM or as a master dual-port RAM in conjunction with the CY7C140-30PC slave dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data, such as cache memory for DSP, bit-slice, or multiprocessor designs. The CY7C140-30PC is available in 48-pin DIP.

Parametrics

CY7C140-30PC absolute maximum ratings: (1)Storage Temperature:–65℃ to +150℃; (2)Ambient Temperature with Power Applied:–55℃ to +125℃; (3)Supply Voltage to Ground Potential (Pin 48 to Pin 24):–0.5V to +7.0V; (4)DC Voltage Applied to Outputs in High Z State:–0.5V to +7.0V; (5)DC Input Voltage:–3.5V to +7.0V; (6)Output Current into Outputs (LOW): 20mA; (7)Static Discharge Voltage: >2001V (per MIL-STD-883, Method 3015); (8)Latch-Up Current: >200mA.

Features

CY7C140-30PC features: (1)True Dual-Ported memory cells which allow simultaneous reads of the same memory location; (2)1K x 8 organization; (3)0.65-micron CMOS for optimum speed/power; (4)High-speed access: 15 ns; (5)Low operating power: ICC = 90 mA (max.); (6)Fully asynchronous operation; (7)Automatic power-down; (8)Master CY7C130/CY7C131 easily expands data bus width to 16 or more bits using slave CY7C140/CY7C141; (9)BUSY output flag on CY7C130/CY7C131; BUSY input on CY7C140/CY7C141; (10)INT flag for port-to-port communication; (11)Available in 48-pin DIP (CY7C130/140), 52-pin PLCC and 52-pin TQFP; (12)Pin-compatible and functionally equivalent to IDT7130/IDT7140.

Diagrams

CY7C140-30PC block diagram

CY7C006
CY7C006

Other


Data Sheet

Negotiable 
CY7C006A
CY7C006A

Other


Data Sheet

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CY7C006A-15AXC

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Data Sheet

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CY7C006A-15AXCT
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Data Sheet

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CY7C006A-20AC
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Data Sheet

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CY7C006A-20AXC
CY7C006A-20AXC

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Data Sheet

0-1: $16.80
1-25: $13.44
25-100: $12.59
100-250: $11.76