Product Summary
The CY7C1382D-200AXC is an 18-Mbit Pipelined SRAM. It integrates 524,288 x 36 and 1,048,576 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The CY7C1382D-200AXC operates from a +3.3V core power supply while all outputs may operate with either a +2.5 or +3.3V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible.
Parametrics
CY7C1382D-200AXC absolute maximum ratings: (1)Storage Temperature:–65℃ to +150℃; (2)Ambient Temperature with Power Applied: –55℃ to +125℃; (3)Supply Voltage on VDD Relative to GND:–0.3V to +4.6V; (4)DC Voltage Applied to Outputs in Tri-State:–0.5V to VDDQ + 0.5V; (5)DC Input Voltage:–0.5V to VDD + 0.5V; (6)Current into Outputs (LOW): 20mA; (7)Static Discharge Voltage: >2001V (per MIL-STD-883, Method 3015); (8)Latch-up Current: >200mA.
Features
CY7C1382D-200AXC features: (1)Supports bus operation up to 250 MHz; (2)Available speed grades are 250, 200 and 167 MHz; (3)Registered inputs and outputs for pipelined operation; (4)3.3V core power supply; (5)2.5V / 3.3V I/O operation; (6)Fast clock-to-output times; (7)Provide high-performance 3-1-1-1 access rate; (8)User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences; (9)Separate processor and controller address strobes; (10)Synchronous self-timed writes; (11)Asynchronous output enable; (12)Single Cycle Chip Deselect; (13)Offered in JEDEC-standard lead-free 100-pin TQFP, 119-ball BGA and 165-Ball fBGA packages; (14)IEEE 1149.1 JTAG-Compatible Boundary Scan; (15)"ZZ" Sleep Mode Option.
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
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CY7C1382D-200AXC |
Cypress Semiconductor |
SRAM 1Mx18 3.3V COM 1CD Sync PL SRAM |
Data Sheet |
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CY7C1382D-200AXCT |
IC SRAM 18MBIT 200MHZ 100LQFP |
Data Sheet |
Negotiable |
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